1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
The related art as a background of the present invention includes US2004/0217358 A1 corresponding to Japanese Patent Application Laid-Open Publication No. 2003-318398 entitled “Silicon carbide semiconductor device”, which was matured from a Japanese patent application No. 2002-125412 filed by the present applicant.
The related art in the publication describes a semiconductor device having a semiconductor substrate including: a silicon carbide substrate region of an N+-type; and an N−-type epitaxial region formed on the substrate region; where the semiconductor device further includes an N−-type polycrystalline silicon region formed to be contacted with a first main surface of the semiconductor substrate in a manner that the epitaxial region and the N−-type polycrystalline silicon layer are connected by heterojunction with each other, so that the N−-type polycrystalline silicon layer acts as a hetero semiconductor region. The semiconductor device further includes a gate electrode formed, via gate insulator layer, near the junction region between the epitaxial region and N−-type polycrystalline silicon region. The N−-type polycrystalline silicon region is connected to a source electrode, and the N+-type silicon carbide substrate region has a reverse surface formed with a drain electrode.
The semiconductor device according to the related art having such a configuration acts as a switch, by controlling an electric potential of the gate electrode in a state that the source electrode is grounded and a predetermined positive voltage is applied to the drain electrode. Namely, a reverse bias is applied to the heterojunction between the N−-type polycrystalline silicon region and the epitaxial region in the state that the gate electrode is grounded, so that no electric current flows between the drain electrode and source electrode. However, in a state that a predetermined positive voltage is applied to the gate electrode, there is generated a gate field acting on the hetero junction interface between the N−-type polycrystalline silicon region and the epitaxial region to decrease a thickness of an energy barrier at the heterojunction plane relative to an interface of a gate oxide film, thereby allowing electric current to flow between the drain electrode and the source electrode.
Note that the related art such as the noted patent publication adopts the heterojunction region as a channel controlling non-conduction and conduction of electric current, so that a channel length is functionally provided substantially at the thickness of the hetero barrier, thereby allowing obtainment of a conduction property of a low resistance.